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STV0297E
QAM demodulator IC with A/D converter
Data Brief
Features

Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams Processes Japanese transport stream multiplex frame (TSMF) High-performance integrated A/D converter suitable for direct IF architecture in all QAM (quadrature amplitude modulation) modes Supports 16, 32, 64, 128 and 256 point constellations Small footprint package: (10 x 10 mm) Very low power consumption Full digital demodulation Variable symbol rates Front derotator for better low symbol rate performance and relaxed tuner constraints Integrated matched filtering Robust integrated adaptive pre and post equalizer On-chip FEC A/C with ability to bypass individual blocks 10 programmable GPIO Two AGC outputs suitable for delayed AGC applications (sigma-delta outputs) Integrated signal quality monitors, plus lock indicator and interrupt function mapped to GPIO pin Improved signal acquisition System clock generated on-chip from quartz crystal Low frequency crystal operations 4, 16, 25 30 MHz 4 I2C addresses Easy control and monitoring via 2-wire fast I2C bus

TQFP64 (10 x 10 x 1.40 mm) Additional I2C bus (I2C repeater) dedicated to tuner control for minimum tuner disturbance Programmable clock derived from system clock and available for external use Parallel and serial output interfaces, with DVB common interface support On chip voltage regulator CMOS technology, 1.0 V operation
Applications

Japan, Europe, Asia cable set-top boxes Cable modems Cable ready TV Cable PC card Cable network module

December 2006
Rev 1
1/5
www.st.com 5
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Description
STV0297E
1
Description
The STV0297E is a complete single-chip QAM (quadrature amplitude modulation) demodulation and FEC (forward error correction) solution that performs sampled IF to transport stream (MPEG-2 or MPEG-4) block processing of QAM signals. It is intended for the digital transmission of compressed television, sound, and data services over cable. It is fully compliant with ITU-T J83 Annexes A/C or DVB-C specification bitstreams (ETS 300 429, "Digital broadcasting systems for television, sound and data services - Framing structure, channel coding and modulation - Cable Systems"). It can handle square (16, 64, 256-QAM) and non-square (32, 128-QAM) constellations. Japanese DBS systems require a transport stream multiplex frame (TSMF) layer to carry digital signals over cable systems. When the recovered transport stream is a multiplex frame, the STV0297E post-processes it to extract a single transport stream. Automatic detection of the TSMF layer is provided. The chip integrates an analog-to-digital converter that delivers the required performance to handle up to 256-QAM signals in a direct IF sampling architecture, thus eliminating the need for external downconversion. The IF can be up to 57 MHz while the STV0297E allows the sampling clock to be freely selected from a given range (and meeting constraints derived from SAW filter and symbol rate characteristics). All further processing is fully digital, so no external feedback loop is required. The STV0297E handles a wide range of symbol rates, ranging from the highest practical rates to rates as low as 0.87 Mbaud, even if there is a significant frequency offset. The STV0297E is thus an excellent candidate for integration in world-wide set-top boxes, cable modems and cable tuners. It provides all demodulation and FEC functions required for the recovery of QAM modulated bitstreams with outstanding BER results. In addition, it includes several features that give simple and immediate access to various quality and status monitoring parameters. The STV0297E also provides outputs, such as delayed AGC or a noise-free IC bus dedicated to tuner control, which simplifies the design of high-quality application boards. These outputs are mapped to a 10-bit GPIO matrix allowing a good optimization of the application PCB. The STV0297E outputs error corrected MPEG transport streams in a wide variety of formats, including the DVB common interface format with programmable data clock frequency. The STV0297E interfaces seamlessly to the packet demultiplexers embedded in the ST backend product families. The dynamic performance of the STV0297E has been significantly improved and is close to theoretical limits thanks to new demodulation algorithms and a wide equalizer allowing the STV0297E to correct both pre and post echoes.
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STV0297E Figure 1. STV0297E block diagram
Description
Initial demodulator Adjacent filter Symbol timing recovery Nyquist filter - Digital AGC Signal quality estimator BER Tester Carrier recovery Phase noise tracker GPIO/AGC1 GPIO/AGC2 GPIO/LOCK GPIO/IT
IB_IN_P IB_IN_M
ADC
AGC and delayed AGC GPIO switching matrix
Pre and post echo adaptive equalizer
Lock status IT generator
GPIO/SCLT GPIO/SDAT GPIO/CS0
I2C Repeater
FEC Annex A and C De-interleaver Reed - Solomon FEC decoder Descrambler
GPIO/CS1 TSMF function
NRESET
to all blocks
Clock generator
IC interface
JTAG controller
Output formatter
A
SDA
SCL
M_VAL
Z0
M_ERR
M_SYNC
M_CKOUT
JTAG[4:0]
TS_DATA[7:0]
3/5
Revision history
STV0297E
2
Revision history
Table 1.
Date 19-Dec-2006
Document revision history
Revision 1 Initial release. Changes
4/5
STV0297E
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